View HI-8050_4558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HI-8050/51, HI-8150/51
January 2001
CMOS HIGH VOLTAGE DISPLAY DRIVER
APPLICATIONS
! Dichroic Liquid Crystal Displays ! Standard Liquid Crystal Displays ! 5 Volt Serial Data to Parallel High Voltage
GENERAL DESCRIPTION
The HI-8050, HI-8051, HI-8150 and HI-8151 are CMOS integrated circuits designed for high voltage LCD display drive applications. The HI-8050 & HI-8051 have TTL logic inputs whereas the HI-8150 & HI-8151 have CMOS logic inputs. They drive up to 38 segments at voltages between +5 and -30 volts. The optional negative converter on the HI-8050 & HI-8150 can be used to generate the negative display drive voltage. All products have test inputs to facilitate opens and shorts testing as well as automatic blanking of the display if the +5V power is lost. The HI-8050 and HI-8150 are designed to replace the HI-8010 and HI-8020 devices in all 5 volt applications. They offer significantly enhanced ESD protection along with a considerably faster serial input data rate. The data is serially clocked into the device on the negative edge of the clock and latched in parallel to the segment outputs on the high to low transition of the load input. Serial output data changes on the positive edge of the clock allowing the cascading ofmultiple drivers for larger displays. The device layout supports all previous pinouts of the HI-8010/HI-8020 products. In addition, new technology and features afford new packaging options. Consult your Holt Sales Representative to explore the possibilities.
PAD CONFIGURATION (Top View)
BPIN BPOSC VDD N/C CONVOSC CONVOUT VEE S37 S38 S1 S2 S3 S4 S5 S6 S7
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
HI-8050PQI HI-8150PQI HI-8050PQT & HI-8150PQT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
S27 S26 S25 S24 S23 S22 S21 S20 DOUT38 DOUT32 DOUT30 T2 T1 N/C BPOUT N/C
(See page 3-32A for HI-8051 & HI-8151 pin configurations)
FEATURES
! 4 MHz serial input data rate ! 38 segment outputs ! Cascadable ! 5 Volt inputs translated to 35 Volts ! Test pins allow hardware all "ON", all "OFF" or alternating ! Monitors 5 volt supply and forces all segments to "OFF" condition if lost ! Negative voltage converter available on-chip ! CMOS low power ! Military processing available
FUNCTIONAL BLOCK DIAGRAM
DIN CL
CS
LD
DATA IN
38 Stage Shift Register
CLK
DOUT38 DOUT32 DOUT30
8020OPT
CONTROL LOGIC
LE
BPIN BPOSC
38 Bit Latch
Oscillator Divider Voltage Translator H i g h Voltage Buffer
Voltage Translators H i g h Voltage Drivers
BPOUT
HOLT INTEGRATED CIRCUITS 1
38 SEGMENTS
(DS8050 Rev. C)
01/01
HI-8050/51, HI-8150/51
PIN DESCRIPTION TABLE
SIGNAL VSS 8020OPT CS CL LD DIN BPIN BPOSC VDD CONVOSC CONVOUT VEE S1 to S38 BPOUT T1 T2 DOUT30 DOUT32 DOUT38 FUNCTION POWER 0 Volts DESCRIPTION
LOGIC INPUT Open or high logic level selects the HI-8010/HI-8110 CL / CS logic. A low selects the HI-8020/HI-8120 Logic (HI-8050 & HI-8150 only) LOGIC INPUT Chip select - Active low LOGIC INPUT Serial data input clock - Active low LOGIC INPUT Latches data in shift register to the segment outputs - Active high LOGIC INPUT Serial input data to the shift register INPUT OUTPUT POWER INPUT OUTPUT POWER OUTPUT OUTPUT Backplane frequency input. Either driven from an external source or connected to BPOSC and an external resistor and capacitor. Internal oscillator pin. Connected to BPIN and an external resistor and capacitor +5V 5%, Positive voltage of the backplane and segments Used in conjunction with CONVOUT to generate the negative VEE voltage on-chip (HI-8050 & HI-8150 only). Used in conjunction with CONVOSC to generate the negative VEE voltage on-chip (HI-8050 & HI-8150 only). Negative voltage of the backplane and segments - between VSS and VDD- 35V Segment outputs to LCD display Backplane output to LCD display (See Figure 3 for cascading drivers)
LOGIC INPUT Used in conjunction with T2 to control display mode. Normal mode is logic low. LOGIC INPUT Used in conjunction with T1 to control display mode. Normal mode is logic low. OUTPUT OUTPUT OUTPUT Logic output from the 30th bit of the shift register. Use for pattern verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only). Logic output from the 32nd bit of the shift register. Use for pattern verification or as the DIN of the next cascaded driver (HI-8050 & HI-8150 only). Logic output from the 38th bit of the shift register. Use for pattern verification or as the DIN of the next cascaded driver.
HOLT INTEGRATED CIRCUITS 2
HI-8050/51, HI-8150/51
FUNCTIONAL DESCRIPTION
INPUT LOGIC The data is clocked into a serial shift register from the DIN input on the negative edge of CL while CS is held low. LD is normally held low and pulsed high only when data from the shift register is parallel latched to the segment outputs. CS must be low when LD is pulsed. The latches are transparent while LD is high. A logic "1" in the shift register causes the corresponding segment output to be out of phase with the BP output. All four logic inputs are TTL compatible on the HI-8050/51and CMOS compatible on the HI-8150/51. BPOSC and BPIN The user has the option of creating the backplane frequency internally or providing a signal from an external source. For an internal oscillator, BPIN and BPOSC are connected together and the appropriate R & C combination is applied as shown in Figure 1. The resulting backplane frequency is approximately: fBP = 1 . (R = 220K, C = 220pF, fBP 100HZ) 256 RC The value of the resistor must be greater than 30K. Alternatively, BPOSC is left open and an external backplane signal of the desired frequency is applied to the BPIN input. VEE & NEGATIVE VOLTAGE CONVERTER VEE can be connected to a negative power supply. Alternatively, the HI-8050 & HI-8150 have the option of generating the VEE voltage with a built-in -25 volt negative voltage converter (See Figure 2). When not used, the open CONVOSC pin is detected and all power consuming circuitry is disabled. The converter will survive a short between two segments and stillmaintain a VEE voltage of -20V. T2 0 0 1 1 T1 0 1 0 1 Display Mode Normal All Off All On Alternating On/Off Segments DOUT The DOUT30, DOUT32, and DOUT38 pins are available for cascading devices to drive more segments (See Figure 3) and for verifying the integrity of the shift register data. The outputs can drive 2 TTL loads. They change on the positive edge of CL. AUTOMATIC SEGMENTS OFF A threshold device detects when the 5V supply is below approximately 1V and forces all the segments and the backplane to the same level. This feature is used to discharge the VEE capacitor when the 5V power is switched off, to prolong the life of the LCD display. 8020OPT The CL and CS inputs function the same as the HI-8010 and HI-8110 product (See Figure 5) if this pin is left open or held high. If held low, the two pins function the same as the HI-8020 and HI-8120 product (See Figure 6). This input is available only on the HI-8050 (TTL) and HI-8150 (CMOS) products. TEST INPUTS The test functions available are:
The test inputs must be tied to the appropriate logic level for correct circuit operation. Both test inputs are TTL compatible on the HI-8050/51 and CMOS compatible on the HI-8150/51.
VDD 68K
C R
CONVOSC
OSC RSENSE Control
/ 256
VDD R BPIN BPOSC TO BACKPLANE TRANSLATOR AND DRIVER Q
IN5818, IN5819
CONVOUT
330H VSS
VDD
C VSS
VEE
10F VSS
Figure 1. INTERNAL OSCILLATOR CIRCUIT
Figure 2. OPTIONAL VOLTAGE CONVERTER
HOLT INTEGRATED CIRCUITS 3
HI-8050/51, HI-8150/51
LD CL CS DIN
BPOUT
CS CL LD DIN DO CS CL LD DIN DO CS CL LD DIN DO
1M 1F
1M 1F
R
BPIN BPOUT
BPIN BPOUT BPOSC
BPIN BPOUT BPOSC
C
BPOSC
1M
SEGMENTS BACK
1M 1F 1F
360p
SEGMENTS
SEGMENTS
PLANE
Figure 3. RC OSCILLATOR AND CASCADED DEVICES
DIN CS CL
Figure 4. OFFSET MEASUREMENT
DATA IN
38 Stage Shift Register
CLK
DOUT
DIN CS CL
DATA IN
38 Stage Shift Register
CLK
DOUT
Figure 5. HI-8010/HI-8110 CL & CS LOGIC (8020OPT = OPEN or HIGH)
Figure 6. HI-8020/HI-8120 CL & CS LOGIC (8020OPT = LOW)
CL INPUT
tCL tCW
DIN INPUT
tDS tDH
CS INPUT
tCSS
tCSH
LD INPUT
tLCS tCSL tLS
VALID
tCDO
DOUT OUTPUT (8020OPT float or high)
tLW
tCDO
DOUT OUTPUT (8020OPT low)
VALID VALID
Figure 7. TIMING DIAGRAM
HOLT INTEGRATED CIRCUITS 4
HI-8050/51, HI-8150/51
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V Supply Voltage VDD ..........................0V to 7V Operating Temperature Range(Industrial) ....... -40C to +85C VEE................VDD-35V to 0V (Hi-Temp/Mil) ..... -55C to +125C
Voltage at any input, except BPIN..-0.3V to VDD+0.3V Storage Temperature .................................... -65C to +125C Voltage at BPIN input ..............VDD-35V to VDD+0.3V Solder Temperature (Leads) ..................... +280C for 10 sec. (Package) ........................................ +220C DC current per input pin .....................................10 mA Power Dissipation............................................500 mW Junction Temperature, Tj .. ........................................ +175C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD = 5V 5%, VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Operating Voltage Supply Current:
(Converter Off, fBP = 0Hz)
Input Low Voltage, HI-8050/51 only (except BPIN) Input High Voltage, HI-8050/51 only (except BPIN) Input Low Voltage, HI-8150/51 only (except BPIN) Input High Voltage, HI-8150/51 only (except BPIN) Input Low Voltage, BPIN Input High Voltage, BPIN Input Current (except T1 & T2) Input Current (T1 & T2) Input Capacitance (Guaranteed, not tested) Segment Output Impedance Backplane Output Impedance Data Out Current: Source Current Sink Current Voltage Converter: @ No Load (VDD - VSS = 5V, TA = 25C) @ 0.1mA Load @ 10KW Load Offset Voltage (Guaranteed, not tested)
VDD IDD IEE VILTTL VIHTTL VILCMOS VIHCMOS VILX VIHX IIN1 IIN2 CI RSEG RBP IDOH IDOL VEEC IDD VEEC VOS
3.0 Static, No Load Static, No Load Logic Inputs Logic Inputs Logic Inputs Logic Inputs
0 2 0 0.7 VDD VEE 0.8 VDD 10 10 450 3.2 -22 -20
VIN = 0V to 5V VIN = 0V to 5V IL = 10A IL = 10A @ 25C VOH = 4.5 VOL = 0.4 See Fig. 2 See Fig. 2 See Fig. 2 See Fig. 4
7.0 200 120 0.8 VDD 0.3 VDD VDD 0.6 VDD VDD 100 10 15 600 -3.0 -21 1.8 25
-21.5
V A A V V V V V V nA A pF KW W mA mA V mA V mV
HOLT INTEGRATED CIRCUITS 5
HI-8050/51, HI-8150/51
AC ELECTRICAL CHARACTERISTICS (See Figure 7)
VDD = 5V 5% , VEE = -25V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER SYMBOL VDD MIN TYP MAX UNITS
Clock Period Clock Pulse Width Data In - Setup Data In - Hold Chip Select - Setup to Clock Chip Select - Hold to Clock Load - Setup to Clock Chip Select - Setup to Load Load Pulse Width Chip Select - Hold to Load Data Out Valid, from Clock
non-cascaded cascaded non-cascaded cascaded
tCL tCL tCW tCW tDS tDH tCSS tCSH tLS tCSL tLW tLCS tCDO
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
250 500 125 250 80 80 100 120 120 0 130 120 170
ns ns ns ns ns ns ns ns ns ns ns ns ns
HI-8051 & HI-8151 PIN CONFIGURATIONS
(See page 3-27 for the HI-8050 & HI-8150 pin configurations)
LD DIN BPIN BPOSC VDD S37 S38 S1 S2 S3 S4 S5 S6
1 2 3 4 5 6 7 8 9 10 11 12 13
HI-8051PQI HI-8151PQI HI-8051PQT & HI-8151PQT
39 38 37 36 35 34 33 32 31 30 29 28 27
S26 S25 S24 S23 S22 S21 S20 DOUT 38 N/C T2 T1 BPOUT S19
HOLT INTEGRATED CIRCUITS 6
HI-8050/51, HI-8150/51
ORDERING INFORMATION
HI - 805xPQx
PART NUMBER I T PART NUMBER 0 1 PART NUMBER HI-805 HI-815 TEMPERATURE RANGE -40C TO + 85C -55C TO +125C PACKAGE DESCRIPTION 64 PIN PLASTIC THIN FLAT QUAD PACK (TQFP) 52 PIN PLASTIC QUAD FLAT PACK ( PQFP) LOGIC INPUT LEVELS TTL CMOS # SEGMENTS 38 38 FLOW I T BURN IN NO NO LEAD FINISH SOLDER SOLDER
HOLT INTEGRATED CIRCUITS 7
HI-8050/51, HI-8150/51 PACKAGE DIMENSIONS
inches (millimeters)
52 PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type: 52PQS
.0256 BSC (0.65 BSC) .520 .010 SQ. (13.2 .25) .394 .004 SQ. (10.00 .10) .012 .002 (.30 .05)
.035 +.006/-.004 (.88 +.15/-.10) .079 .002 (2.00 .05)
See Detail A
.096 MAX. (2.45 MAX. ) .008 R TYP. (0.20 R TYP.)
.012 R TYP. (0.30 R TYP.)
0 7 .010 to .020 (0.25 to 0.50)
DETAIL A
64 PIN PLASTIC THIN QUAD FLAT PACK (TQFP)
Package Type: PackageType: 64PTQS
.354 .008 SQ. (9.00 .20)
.276 .004 SQ. (7.00 .10)
.0157 BSC (0.40 BSC) .007 .004 (0.18 .05) .024 +.006/-.004 (0.60 +.15/-.10)
.055 .002 (1.4 .05)
.008 R TYP. (0.20 R TYP.)
See Detail A
.063 MAX. (1.60 MAX.) .004 .002 (0.10 .05) .008 R TYP. (0.20 R TYP.) 0 7
Detail A
HOLT INTEGRATED CIRCUITS 8

▲Up To Search▲

Price & Availability of HI-8050

	To Download HI-8050 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .